IP核 tb_com
module tb_com();reg ad9361_l_clk,rst; initial beginad9361_l_clk0;forever #4.545 ad9361_l_clk~ad9361_l_clk;
end
initial beginrst1;#9.09 rst0;
end
wire [63 : 0] m_fll_phase_shift_dout; // fll 输出 dout
// FLL Phase Shift
com_cmpy_a12_b12 FLL_P…